The present invention relates to a memory controller for controlling and interfacing digital memory used in digital video processing.
Techniques for digital transmission of video promise increased flexibility, higher resolution, and better fidelity. Recent industry collaborations have brought digital video closer to reality; digital video transmission and storage standards have been generated, and consumer digital video products have begun to appear. The move toward digital video has been encouraged by the commercialization of digital technologies in general, such as personal computers and compact discs, both of which have increased consumer awareness of the possibilities of digital technology.
Personal computers, which have recently become common and inexpensive, contain much of the computing hardware needed to produce digital video, including a microprocessor/coprocessor for performing numeric calculations, input and output connections, and a large digital memory for storing and manipulating image data. Unfortunately, personal computers are not suitable for consumer digital video reception, because the microprocessor in a personal computer is a general purpose processor, and typically cannot perform the calculations needed for digital video fast enough to produce full-motion, high definition video output.
Accordingly, there is a need for a special purpose processor particularly suited for performing digital video-related calculations, which can be used as a digital video receiver in consumer applications. Since costs can be most effectively contained by using standard personal computer components where possible, there is a further need for a special purpose microprocessor which facilitates use of commercially available and inexpensive computer components such as digital memory chips. At the same time, however, the special purpose processor must be sufficiently flexible to use any of the available variety of digital memory chips at or near their maximum speed.
In accordance with the present invention, the above needs are met by a special purpose processor for performing computations needed for digital video reception, which is equipped with a memory interface facilitating use of standard computer memory components in connection with the special purpose processor, to thus reduce the attendant costs.
The special purpose processor includes a data buffer used, e.g., in buffering data delivered through the memory controller. The buffer includes 2n memory locations for storing data, each memory location being associated with an n-bit binary address. An n+1-bit binary write address and an n+1-bit binary read address are used to access the buffer. These addresses are compared to each other to determine whether there is space in the buffer, and whether data is available to be read from the buffer. When data is to be stored in the buffer, the data is stored at the memory location associated with n selected bits of the n+1-bit binary write address, and the n+1-bit binary write address is incremented; when data is read from the buffer, the data is read from the memory location associated with n selected bits of the n+1-bit binary read address, and the n+1-bit binary read address is incremented.
In accordance with principles of the present invention, the data buffer is specially configured to permit a different clock to be used by the memory circuit attached to the memory controller, than is used in the remainder of the processor. Because two different clocks are used, the n+1-bit binary read address and n+1-bit binary write address might be incremented in an asynchronous fashion. A concern this raises, is the possibility that an address will be undergoing a logical transition, and thus may have one or more bits with undetermined logical states, at the moment the logic circuitry is comparing the two addresses to determine if space is available in the buffer and/or whether data is in the buffer and available for output. Uncertainty in this comparison could result in data being unintentionally overwritten, or invalid data being unintentionally read.
In accordance with principles of the present invention, such consequences are avoided by deriving the n+1-bit binary write address and n+1-bit binary read address from n+1-bit Gray-coded counters. A characteristic of Gray-code format is that, when a Gray-coded counter is incremented, only one bit changes value. This feature of the Gray-code format is of particular significance because it means that, when the Gray-coded counters are incremented, only one bit in the address changes value, and thus only one bit will have an undetermined logical state. Accordingly, if a counter is undergoing a logical transition at the moment the logic circuitry is comparing a read and write address, any uncertainty in the comparison will not result in adverse consequences.
In specific embodiments, the Gray-coded n+1-bit binary write counter, and the Gray-coded n+1-bit binary read counter, are mapped to corresponding n+1-bit write and read addresses by forming a bit of the write and read address from a logical function of bits of the corresponding counter. As a result, the determination of whether the buffer is full or empty is simplified. Specifically, the buffer is full when the most significant bit of the n+1-bit binary write address is not equal to the most significant bit of the n+1-bit binary read address, and the n least significant bits of the n+1-bit binary write address are equal to the n least significant bits of the n+1-bit binary read address. Further, the buffer is empty when the most significant bit of the n+1-bit binary write address is equal to the most significant bit of the n+1-bit binary read address, and the n least significant bits of the n+1-bit binary write address are equal to the n least significant bits of the n+1-bit binary read address. When neither condition is met, the buffer is neither full nor empty.
To reduce the potential for metastability, the n+1bits of the Gray-coded read counter are passed through two latches, which are clocked by the same clock used by the processor, and the output of the second latch is used to determine whether to write data into the buffer. Similarly, the n+1bits of the Gray-coded write counter are passed through two latches, which are clocked by the same clock used by the memory circuit, and the output of the second latch is used to determine whether to read data from the buffer.